1. Field of the Invention
The present invention relates to a method for producing chip stacks and to chip stacks formed by stacked integrated devices.
2. Description of the Related Art
In order to further reduce the size of integrated systems, integrated devices, e.g., chips are arranged in stacks. Each of the integrated devices comprises contact pads thereon which are bonded to a system PCB (printed circuit board). In between the integrated device chips, an insulating spacer has to be provided to enable the bond wire to contact the contact pads and to avoid shortcuts with the respective upper integrated device chip.
Particularly for integrated device chips with a small thickness, e.g. below 100 μm, the stack height is therefore dominated by the thickness of the spacer. In addition, the handling and the assembly of the integrated device stack is more challenging if the stack height is increased due to the provision of the spacers compared to stacks that do not comprise spacers. Also, the length of the bond wires is higher in a chip stack having spacers than in a chip stack without spacers which leads to a reduced electrical performance of the chip stack system. Furthermore, the thermal resistance of an integrated device stack having spacer in the integrated device chips is increased.
Moreover, conventional integrated device stacks are prone to produce electrical shorts of the bond wires while applying the spacer material and while positioning an integrated device onto the spacer material. This reduces reliability and yield of production.